MAESTRO: Dynamic Runtime Power and Concurrency Adaptation

Microprocessor core counts are on a trajectory such that for many applications the microprocessor will soon be overprovisioned for computation with respect to off-chip communication and memory system capabilities. In the absence of strategies to exploit intra-chip communication, performance of even simple benchmarks is noticeably impacted by coscheduling multiple copies on the cores of current system and the problem will get worse. We are developing the MAESTRO runtime system to experiment with the idea of dedicating excess computational resources to (1) to reduce power consumption of memory bound applications with little performance impact, (2) provide guidance to adaptive concurrency control to improve performance, and (3) isolate the performance monitoring and other system activities to reduce the effects of “jitter” on tightly-coupled applications. We describe initial experiments in which we dedicate one core to monitor chip-wide bottlenecks using hardware performance counters. When bottlenecks in the memory system are approached, the frequency (and power) of the cores are reduced. The MAESTRO prototype runs on an AMD Phenom as a Linux daemon pinned to one core while applications are pinned to the remaining cores. On a desktop system, running at low frequency can save up to 36% of the total power consumed with minor performance degredation. MAESTRO allows single core jobs to compute at full frequency and saves power when the bottlenecks exist during parallel execution. We present motivating experiments, describe aspects of the working prototype of MAESTRO, and present some early results.